Synplicity’s Synplify DSP 3.6 Software Speeds DSP Algorithm Design for ASICs and FPGAs

The Synplify DSP tool provides a unique ESL synthesis methodology that realizes significant productivity and portability advantages over traditional HDL design flows. System and algorithm designers quickly can capture complex algorithmic behavior using the Synplify DSP library which includes powerful modeling features such as vector arithmetic, fixed-point precision up to 128-bits, and a rich set of IP cores. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed-optimized RTL implementations from a single model. This eliminates the burden of hand coding functions and architectural optimizations, achieves significantly faster design capture, speeds time to market and enables rapid design exploration that results in improved quality and lower cost.

Synplicity has enhanced the optimization engine to recognize repeating patterns of operations in the design, and apply time-multiplexed scheduling to reduce the implementation area. This results in much lower area across a broader set of algorithm designs. This technique is ideal for designers working on applications such as wireless, radar, and digital video compression which typically require patterns that are highly replicated.

Our architectural synthesis methodology will serve the needs of designers developing systems where parallelism and multiple sample rates are the design paradigm, says Chris Eddington, Synplicity's director of DSP Marketing. These include applications in wireless, radar and video compression, where multiple instances of IIR, FIR filter banks and multiple channels of any type of filter block are in use. Our architectural optimizations can reduce real estate by as much as 90 percent.