Synplicity's latest DSP Synthesis Engine Targets ASIC Designs

The Synplify DSP ASIC Edition's unique DSP synthesis optimizations automatically implement algorithms allowing designers to explore speed and area tradeoffs, often leading to significant area and timing improvements over hand-coded approaches. Because of this automation users can capture
designs, explore implementation architectures and target them to FPGAs or their chosen ASIC technology. This results in significant productivity improvements often achieving 10 to 20x less development and verification time than otherwise required. Those who have used the beta product have
experienced considerable advantages over traditional handcrafted flows.

For ASIC technologies, the Synplify DSP ASIC Edition has additional features to provide seamless integration of memory and RTL into standard ASIC design flows. For ASIC designs using compiled memories, the Synplify DSP ASIC Edition automatically extracts and manages the memory in a
separate level of hierarchy. This allows the user to easily instantiate memory modules from any 3rd party memory vendor and verify the complete model at the RT level. As a result, the Synplify DSP ASIC Edition provides a solution that integrates well with familiar downstream logic synthesis
and verification flows.

Our Synplify DSP software has been tremendously successful among FPGA users who have experienced significant quality of results benefits, and we are eager to bring the same capabilities to ASIC users, said Andy Haines, senior vice president of marketing, Synplicity. We believe the
performance and productivity benefits offered by our Synplify DSP ASIC Edition software are so significant that it will become the technology of choice when designers implement DSP capabilities into either FPGA or ASIC hardware.

From a single model, the Synplify DSP ASIC Edition software can automatically implement optimized architectures of algorithms into either FPGA or ASIC devices. For teams developing ASICs, the combination of Synplify DSP ASIC Edition and Synplicity's ASIC verification product suite
allows users to quickly verify their ASIC designs in FPGAs at high speed. By prototyping ASIC designs in FPGAs functional bugs can be detected more rapidly and more complex interactions can be observed due to the high operating speed (typically above 100 MHz) of the FPGA.

The software also supports third-party logic synthesis flows from Synopsys, Cadence and third-party ASIC memory IP providers. The Synplify DSP ASIC Edition software provides users with a fully integrated solution with standard ASIC flows.