Synplicity Introduces System Designer: System-Level Implementation and IP Integration Tool for FPGA Design

System Designer is a key component of Synplicity’s ReadyIP Initiative, a program that takes aim at simplifying the access, evaluation and use of IP for FPGA-based system designs. The ReadyIP program allows users to evaluate and “try-before-they-buy” IP within their designs through System Designer using Synplicity’s industry-leading synthesis tools; (see related press release: Synplicity Launches ReadyIP Program: The Industry’s First Universal, Secure IP Flow For FPGA Implementation).

“FPGAs have evolved into system-implementation vehicles by virtue of the increased density, speed, dedicated resources and the time-to market advantages that the latest generation of programmable devices provides,” said Angela Sutton, senior product marketing manager, Synplicity. “The System Designer capability answers customers’ needs for system-level implementation tools by allowing them, for the first time, to access IP from a range of vendors, evaluate the IP in the context of their design and then easily implement the system in their choice of FPGA,” Sutton added.

The System Designer tool accepts as input IP, which complies with the SPIRIT Consortium’s IP-XACT standard for describing IP, and outputs top-level RTL and a Synplify project file ready for synthesizing the complete design. Third-party IP is available to System Designer users via Web browser access integrated into Synplicity’s synthesis products. Through the Synplify Pro and Synplify Premier FPGA design implementation tools, designers using the System Designer capability can browse and download IP from Synplicity partners participating in the ReadyIP program, currently ARM, CAST, Gaisler Research, and Tensilica, and thus easily evaluate various options for their FPGA designs.

System Designer is built on the open source Eclipse, a de facto standard providing for exceptional extensibility. Additionally, the System Designer capability allows Synplify Pro and Synplify Premier users to maintain and deploy internally developed system-level building blocks and components which have been converted to the IP-XACT format, and then re-use them across multiple designs and multiple generations of FPGA designs.

“Synplicity’s System Designer is a step forward for systems designers targeting FPGAs,” said Graham Budd, EVP and general manager, Processor Division, ARM. “Customers will be able to download an evaluation version of the ARM® Cortex™-M1 processor and quickly configure and connect peripheral IP and then automatically generate design descriptions ready for synthesis using Synplify Pro or Synplify Premier. We believe it will be a great benefit to both FPGA system designers as well as our IP users. ”

“We’ve been working closely with Synplicity over the past year as the System Designer tool was in development,” stated Steve Roddy, Tensilica’s vice president of marketing and business development. “We believe that System Designer will boost designer productivity, enabling FPGA designers to focus more time on system analysis and less effort on system construction.”