Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories

The Galaxy Characterization Solution is based on Synopsys' golden-accuracy HSPICE® circuit simulation, technology-leading StarRC™ extraction, NanoTime transistor-level timing and Liberty™ NCX library modeling technologies. The compact CCS models generated by the solution feed seamlessly into the IC Compiler physical implementation and PrimeTime® signoff tools, enabling designers to quickly achieve timing closure and improve productivity.

As process geometries shrink to 28 nanometers (nm) and below and clock frequencies rise, it is essential to account for signal integrity (SI) and variation effects in the timing and noise model libraries to ensure proper silicon performance. As a result, library sizes can quickly explode from tens of gigabytes to hundreds of gigabytes. This poses a dilemma for the designer who needs accuracy but can't handle the enormity of the library or a potential increase in run time. To address this, Liberty NCX generates a compact CCS model that can reduce the library size by an average of 4X without impacting accuracy. In addition, Liberty NCX has been tuned for noise model generation, resulting in up to a 7X speedup. PrimeTime and IC Compiler readily process the compact CCS format, saving valuable run time, disk space and, ultimately, engineering costs.

Synopsys' unique combination of technology and innovative methodologies enables the Galaxy Characterization Solution to deliver a comprehensive characterization capability that covers all aspects of designers' needs, said Dr. Antun Domic, senior vice president and general manager, Synopsys Implementation Group. High-precision compact CCS models for power, timing and noise, combined with the seamless handoff to PrimeTime and IC Compiler allow designers to implement their SoC designs with a high degree of confidence.

Today, the Galaxy Characterization Solution supports timing, power and noise models for standard cell libraries. Upcoming releases will provide timing and noise models for complex macros and embedded memories and will employ the NanoTime static timing engines to generate the results.