Successful tape out of next-generation Arm mobile SoCs

As part of the collaboration, Cadence has fine-tuned its digital and verification full flows on 5nm and 7nm process technologies to drive adoption of the new Arm mobile solution on the Armv9 architecture. In addition, Cadence delivered 5nm and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) to enable customers to achieve optimal power, performance and area (PPA) and accelerate time to tapeout.

Cadence delivered a highly tuned digital flow and corresponding 5nm and 7nm RAKs for the development of SoCs based on the latest Arm mobile solution. The complete, integrated RTL-to-GDS RAKs include the Cadence Modus DFT Software Solution, Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking and Conformal Low Power.

The digital full flow offers Arm mobile solution adopters several capabilities to improve productivity. For example, the Cadence iSpatial technology provides an integrated, predictable implementation flow so users can achieve faster design closure.

The flow also incorporates an innovative hierarchical technology to deliver optimal turnaround time on large high-performance CPUs. The Innovus Implementation System’s GigaOpt power optimisation capability significantly reduces dynamic power consumption. Finally, the Tempus ECO Option provides signoff-accurate final design closure using path-based optimisation, which enables users to achieve PPA targets.

Cadence also optimised its System-Level Verification IP (System VIP) and verification full flow to support the latest Arm AMBA protocols, enabling rapid and dependable adoption of Armv9 IP while accelerating integration and functional signoff of Arm mobile SoCs. Cadence System VIP extensions for Armv9 include new checkers, verification plans and traffic generators to efficiently verify Arm mobile SoC coherency, performance and Arm SystemReady compliance.

The verification full flow, which provides optimal verification throughput for the latest Armv9 IP, includes the Cadence Xcelium Logic Simulation Platform, Palladium Z1 and Z2 Enterprise Emulation Platforms, Protium X1 and X2 Enterprise Prototyping Platforms, JasperGold Formal Verification Platform, vManager Planning and Metrics, and Perspec System Verifier and Virtual System Platform.

“Based on the new Armv9 architecture, the Arm Total Compute solution is designed to enable best-in-class products, allowing our customers to achieve greater performance and efficiency when creating next-generation mobile SoCs,” said Paul Williamson, Senior Vice President and General Manager, Client Line of Business, Arm. “By continuing our work with Cadence, we’re making it easier to unlock the flexibility and performance of our latest CPU and GPU technology to achieve design success and get to market faster.”

“Cadence has collaborated with Arm on many generations of CPUs and GPUs for mobile IP development, and our latest work expands our support for the recently introduced Armv9 architecture,” said Dr. Chin-Chi Teng, Senior Vice President and General Manager, Digital & Signoff Group at Cadence. “Arm uses our Cadence digital and verification full flow innovations to develop its mobile IP, and with the rollout of Arm’s new CPUs and CPUs, we’re enabling customers to achieve PPA targets to accelerate time to tapeout and providing SystemReady verification and early software bring-up.”

The Cadence digital full flow enables customers to achieve PPA goals, and the verification full flow provides improved verification throughput. The flows support the broader Cadence Intelligent System Design strategy, enabling customers to achieve design excellence.