Structured ASICs with Embedded PCI Express PHY

Fabricated in a high performance, eight-metal 0.13-µm process, the CX6100 devices accelerate time-to-market and eliminate many of the risks associated with traditional Standard Cell ASIC development by integrating a silicon-proven PCI Express (PCIe) PHY core.

The twelve devices in the new CX6100 family support a wide range of applications in computing, storage, instrumentation and networking. The embedded PCIe PHY is compliant with the current 1.1 version of the specification and is available in 1, 4, and 8 lane options. Along with the embedded PHY, ChipX is offering an optional PCIe-compliant controller. The PHY offers complete PIPE interoperability for customers wishing to use their own PCIe controller.

With a Standard Cell ASIC, development cycles are long and PHY integration risk is high. By embedding a silicon-proven PCIe PHY that is supported by compliance testing and an optional controller, the CX6100 family eliminates the complexity and risk associated with integrating IP from multiple vendors and allows designers to rapidly develop solutions that keep pace with the evolving standard.”

With the optional PCIe 1.0a compliant controller, designers can quickly develop root port, bridge and endpoint designs. The controller supports 1, 4 or 8 lanes, up to 8 VCs and up to 6 BARs. It features configurable retry buffers and support for up to 4 KB payload sizes. The controller is supplied complete with simulation models, driver software examples and all documentation.

Devices in the CX6100 family offer densities ranging from 240K to 1.8M ASIC gates, up to 1.1Mbits of embedded SRAM and maximum operating frequencies up to 250MHz across the die. Four on-chip, configurable, low-jitter PLLs support output frequencies from 10 MHz to 1 GHz.

According to ChipX, customers can receive tested prototypes in as little as four weeks. Pricing for the CX6100 devices starts under $7 in volumes of 100,000.