Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development

Part of the Cadence System Development Suite, JasperGold Apps perform multiple formal-based verification tasks and leverage a common formal verification platform, database and user interface. JasperGold Apps automate property creation for many common verification tasks, enabling rapid adoption by both design and verification engineers without previous formal experience. All JasperGold Apps leverage the Cadence Jasper Visualize™ graphical visualization and debug technology for fast debugging and a consistent user experience.

Verification of configurable interfaces is a challenging task, as traditional simulation environments aren’t well suited to handle their complexity. Exhaustive verification of highly configurable on-chip networks that integrate multicore SoCs requires both stimulus-driven simulation and formal proof technologies. To ensure the highest quality IP, the network transactions must be checked across communication protocol boundaries. Simulation alone is insufficient to fully check the transfer function of the network.

JasperGold readily accepts commonly available formats like SystemVerilog Assertions (SVA) as its input and has easily scripted setup controls, enabling easy integration with other verification environments. By allowing Sonics to use exactly the same SVA protocol checkers for both simulation and formal verification, the use of JasperGold Apps can help eliminate an entire class of bring-up and ongoing issues.

“The JasperGold Apps are a must-have for IP suppliers and chip designers building SoCs with on-chip networks,” said Drew Wingard, CTO of Sonics. “The JasperGold Apps fit well in our verification methodology and can enable us to achieve the IP quality and integrity our customers expect from the market leader in on-chip networks.”