Solution delivers up to three times reduction in SoC test time

3rd February 2016

Nat Bowers

0 0

Cadence Design Systems' Modus Test Solution enables design engineers to achieve up to a three times reduction in test time, thereby reducing production test cost and increasing silicon profit margins. This next-gen solution incorporates patent-pending, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400 times without impacting design size or routing.

To address the challenges that come with testing designs, the Cadence Modus Test Solution includes the following innovative capabilities:

2D compression: Scan compression logic forms a physically aware 2D grid across the chip floorplan, enabling higher compression ratios with reduced wirelength. At 100 times compression ratios, wirelength for 2D compression can be up to 2.6 times smaller than current industry scan compression architectures.
Elastic compression: Registers embedded in the decompression logic enable fault coverage to be maintained at compression ratios beyond 400 times by controlling care bits sequentially across multiple scan cycles during Automatic Test Pattern Generation (ATPG).
Embedded memory bus support: A shared test access bus can be inserted to perform at-speed Programmable Memory Built-In Self Test (PMBIST) across multiple embedded memories in an IP core. New soft programmable test algorithms for FinFET SRAMs and automotive safety applications are also included with this feature.
Powerful common scripting and debug environment: Design For Test (DFT) logic insertion and ATPG capabilities use a new, unified Tcl scripting and debug environment that is shared with the Cadence Genus Synthesis Solution, the Innovus Implementation System and the Tempus Timing Signoff Solution.

Dr. Anirudh Devgan, Senior Vice President and General Manager, Digital and Signoff Group, Cadence, commented: “Our next-gen Modus Test Solution delivers new, innovative patent-pending technology that fundamentally changes the way design and test engineers address the test problem. By using a physically aware approach in a 2D grid, and compressing patterns sequentially as well, the Modus Test Solution can significantly reduce digital test time in comparison to traditional approaches, thereby giving Cadence customers yet another significant profitability advantage."

“Minimising the cost of test is crucial in high-volume, price-sensitive markets like embedded processing. The Modus Test Solution is showing a 1.7 times reduction in digital test time on one of our largest and most complex embedded processor chips without any impact on design closure,” added Roger Peters, MCU Silicon Development, Texas Instruments.