Software increases security for FPGA designs

“The release of our Libero SoC v11.7 software offers a significantly improved user experience due to a new and enhanced constraints flow with a new constraints management view, a fully redesigned ChipPlanner and a new simultaneous switching noise (SSN) analyser,” said Jim Davis, Vice President of software engineering, Microsemi. “Customers will also benefit greatly from SmartDebug updates with improved navigation of the user’s design, an improved remote workflow installation and a Serialiser/Deserialiser (SerDes) BER calculator. Additionally, productivity has been greatly accelerated with a SmartTime UI that is two times faster and the SmartPower tool working five times faster in processing designs.”   

In addition to the usability features, which support faster time-to-market for designers of FPGA-based solutions, Microsemi’s Libero SoC v11.7 release also marks the production release of its Secured Production Programming Solution (SPPS) which is used to prevent overbuilding, cloning, reverse engineering, malware insertion and other security threats.

Libero v11.7 introduces an enhanced constraints flow aimed at simplifying the management of all constraints in a design. The solution is used to manage timing constraints, input/output (I/O) attribute constraints, floor planning constraints and netlist attribute constraints to ensure they can be created, imported, edited and organised in a single view. Timing constraints only need to be entered once and can be automatically applied in synthesis, timing-driven place and route and timing verification. Timing constraints for known hardware blocks and intellectual property (IP) elements are derived automatically.

The software release also features a fully redesigned ChipPlanner, a floor planning tool used to define and assign logic to regions within the FPGA. This design technique is particularly useful for controlling design placement in order to obtain optimal results. The ChipPlanner also includes interface updates and significant runtime enhancements, most notably on large and highly utilised designs.

For the SmartFusion2, IGLOO2, and RTG4 families, SmartDebug allows unprecedented visibility into FPGA designs without the need to reinstrument and rebuild the design. With SmartDebug, users can read and write to any FPGA fabric flip-flops using active probes, or view any two flip-flops on the PRA/PRB pins via an external scope using live probes. In addition SmartDebug allows users to read and write to LSRAM, uSRAM and SerDes control registers. In Libero SoC v11.7, Microsemi is further enhancing SmartDebug with uniform fabric probe selection and design navigation for active or live probes, and a standalone version which allows for a lightweight lab installation.

According to the Aberdeen group, by the year 2020 approximately 50bn machines will be connected. Not only do these machines need to be secure, they need to be secured at the device, design and system levels.

Libero v11.7 introduces the company’s SPPS, which enables secured production programming of Microsemi’s SmartFusion2 SoC FPGAs and IGLOO2 FPGAs. SPPS securely generates and injects cryptographic keys and configuration bitstreams into Microsemi’s FPGAs which could prevent cloning, reverse engineering, malware insertion, leakage of sensitive intellectual property (IP) such as trade secrets or classified data, overbuilding and potentially protect against other security threats.

Microsemi’s SPPS uses Federal Information Processing Standards (FIPS)-certified hardware security modules (HSMs) for critical computations, in conjunction with Microsemi’s tamper-resistant flash FPGAs. This prevents today’s major security threats by external adversaries or competitors, unscrupulous contract manufacturers and their employees, or other insiders.

Libero SoC v11.7 also includes several other updates, some of these are mentioned below.

• SSN analyser tool support to compute noise margin for each FPGA pin
• Five times runtime improvement on SmartPower
• Two times user interface (UI) runtime improvement on SmartTime
• Multi-corner analysis support for SmartTime
• Cross clock domain optimisation in physical design