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Silicon Frontline Technology Improves Performance and Capacity of Flagship EDA Products for Post-Layout Verification, 3D Extraction, Nanometer Design

22nd February 2010

Silicon Frontline Inc

ES Admin

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Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company in the post-layout verification market, announced today that new versions of its flagship post-layout verification products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices, are shipping now. F3D improves its performance by up to 10x when compared to the previous version. F3D and R3D also accommodate larger designs than the previous versions announced in May 2009.

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According to Dermott Lynch, VP Marketing at Silicon Frontline, “To address our customers’ post-layout verification needs as their technology options change, we are focused on improving our software products’ performance and our products’ capacity to handle full-chip designs.”

F3D is chosen for providing nanometer and Analog Mixed Signal (A/MS) design accuracy and R3D for its ability to improve the reliability and efficiency of semiconductor power devices.

F3D and R3D incorporate patent-pending 3D technology to deliver a Guaranteed Accurate solution for full-chip, post-layout verification. They work in industry standard flows allowing simpler adoption and quicker closure, with guaranteed accuracy, of the post-layout verification loop.