Signoff tools reduce 28nm SoC time to tapeout by 33%

In addition, UMC achieved a dynamic power consumption of less than 200mW, which represents a 20% reduction over their previous flow. The SoC offering targets entry-level smartphones, tablets, high-end wearables and other advanced mobile devices.

Use of the multi-threaded Encounter Digital Implementation System, which incorporates GigaOpt route-driven optimisation alongside CCOpt concurrent clock data path optimisation, resulted in faster turnaround time with significantly improved performance, die area and dynamic power. The integration of Cadence's Tempus Timing Signoff, Voltus IC Power Integrity and Quantus QRC Extraction Solutions, Physical Verification System, Litho Physical Analyser and CMP Predictor allowed UMC to perform signoff checks much earlier in the process to affirm that the design functioned as intended upon completion.

“The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation and closure so we could quickly deliver a quality reference design to market that exceeded our power, performance and area expectations,” said Shih Chin Lin, Senior Division Director, IP Development and Design Support Division, UMC. “Our mobile customers have very specific device requirements, and we’ve tested the chip to ensure that they have a reliable 28nm silicon-ready reference design.”