Cadence Physical and Electrical DMF Signoff adopted by UMC

19th July 2013

Nat Bowers

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Cadence Design Systems reveal that after extensive benchmark testing, semiconductor foundry United Microelectronics Corporation has adopted the Cadence “in-design” and signoff design-for-manufacturing flows to perform physical signoff and electrical variability optimization for 28nm designs. The flows address both random and systematic yield issues, providing customers with another proven foundry flow for 28nm designs.

Developed in collaboration with UMC, these new flows incorporate the industry’s leading DFM prevention, analysis, and signoff capabilities, including Cadence Litho Physical Analyzer (LPA), Cadence Pattern Analysis, Cadence Litho Electrical Analyzer (LEA), and Cadence Chemical-Mechanical Polishing Predictor (CCP) technologies.

At 28nm and beyond, it is critical to accurately predict and automatically fix DFM “hotspots” to accelerate time-to-yield. UMC joins a growing list of leading foundries standardizing on Cadence DFM solutions to boost productivity and yield for customers. The DFM signoff technologies tightly integrate into the Encounter® digital and Cadence Virtuoso® custom/analog implementation and sign-off solutions. This solution delivers a “correct-by-design” capability for customers that models and analyzes the physical and parametric impact of lithography, CMP, and layout dependent effects, and then optimizes the implementation to mitigate the physical and electrical variation on the designs, allowing users to reach their time-to-volume goals.

“To meet our time-to-market goals, DFM solutions at 28nm need to deliver low cost of ownership, accurate silicon predictability and high performance,” said S.C. Chien, vice president of IP & Design Support division at UMC. “After rigorous evaluation, the Cadence DFM technology was selected for its exceptional characteristics in both physical and electrical DFM analysis. Now, we can offer our customers much greater predictability and faster turnaround time for their advanced node designs.”

“At advanced nodes, prevention of potential DFM hotspots and yield limiters before tapeout is imperative to achieving first-silicon success and the highest silicon yields,” said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. “Working in tight partnership with UMC, we continue to invest in technologies that strengthen our leadership in sign-off technologies, like providing DFM-aware implementation flows for current and future nodes.”