Samsung solution leverages Mentor Graphics tools

The Samsung solution extracts customer yield-averse design patterns, feeds that information forward to optimise manufacturing and testing, and closes the loop with feedback from silicon results for product design and yield improvement. This solution is not only useful to initial customer designs, but it also allows learnings from current production designs to be applied to next-generation designs from that same customer across entire product families.

“Samsung is committed to helping our customers to ramp up as quickly as possible and get to market faster with their semiconductor designs,” said JaeHong Park, senior vice president, Design Services, Samsung Foundry. “Our Closed-Loop DFM solution, which is built on top of Mentor platforms, gives our customers deeper, faster insight into design hotspots, improving quality and yield. Our work has shown more than 10% product yield gains in the initial phase of production when compared to the same design without our Closed-Loop DFM system applied.”

“This new use model for the Calibre and Tessent platforms is another milestone in our continued partnership with Samsung,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “Our joint customers can use Closed-Loop DFM with production Calibre and Tessent software to deliver leading-edge products faster on all of Samsung’s process nodes.”

The pre-manufacturing flow in Closed-Loop DFM, called PRISM (Pattern Recognition & Identity Scoring Method), analyzes an IC design by deconstructing it into layout patterns and, using the Calibre Pattern Matching™ solution, identifying patterns known to have been yield detractors in the past. Samsung then uses Calibre LFD software along with other Calibre DFM products to spot previously unknown potential lithography hotspots and analyze their likely impacts on manufacturability. Samsung and the customer jointly make the best use of PRISM results to determine design and/or manufacturing changes needed to ensure that the customer’s unique design style achieves target yields and reduces production ramp variability.

After manufacturing, a second Closed-Loop DFM flow called FLARE (Failure anaLysis And yield Rank Estimation with DFM hotspot database) identifies yield-limiting layout patterns based on silicon results. Fail data from wafer test are diagnosed by the Foundry customer and analyzed by Samsung Foundry to identify unique layout patterns that cause yield loss. Samsung and its customers use this information to analyse systematic issues caused by physical design features to improve the ramp-up speed for design re-spins, as well as for new designs using the same IP blocks and or subsystems.

Samsung Foundry also uses FLARE data to improve its DFM kits to share silicon findings with customer designers. FLARE uses the Tessent Diagnosis tool for layout-aware diagnosis, the Calibre Pattern Matching solution for generating a hotspot database, and statistical analysis in the Tessent YieldInsight product to identify the yield limiting layout patterns.

The Closed-Loop DFM flows are in production use today for customers of Samsung Foundry services. While proven in 14 nm technology, the flows can be used for ICs manufactured with other Samsung process nodes.

At the 2016 Design Automation Conference, Mentor and Samsung are co-hosting a lunch seminar entitled “Accelerate Yield Ramps with Samsung Foundry Closed-Loop DFM and Mentor Tools.” The event is Monday, June 6, from 12:00 to 1:30 PM. Interested customers can register for the event using this registration link.