RTXC RTOS supports high-performance ARM Cortex-A8 core

Known for its efficiency, high performance and small footprint, the RTXC family of RTOSes from Quadros Systems provides a low-overhead, flexible solution for customers working on OMAP35x and ARM Cortex-A8 based designs. Quadros Systems offers one-stop development and run-time solutions which include the RTXC RTOS and ARM RealView development tools. This integrated and supported solution from Quadros Systems gives developers a single point of contact for high quality tools and foundational software.

“With the RTXC Quadros RTOS, developers working on OMAP35x-based embedded applications, such as industrial automation, point-of-sale terminals or patient monitoring devices, can now take full advantage of a powerful processing platform that provides application-tuned peripherals, high performance and low power consumption in a single solution,” said Stephen Martin, vice president, sales and marketing for Quadros Systems.

For RTOS porting, Quadros utilized TI’s OMAP 3 platform, which delivers more than four times the processing power of today's 300MHz ARM9 devices, giving developers access to laptop-like performance at handheld power levels. Quadros engineers used the popular OMAP35x processor-based BeagleBoard (www.beagleboard.org) and RealView tools from ARM to complete the development environment.

“Having RTXC Quadros RTOS support on TI’s OMAP35x provides embedded designers with increased options and flexibility to efficiently and cost-effectively run new applications and develop new features that are best suited for our portfolio of ARM Cortex-A8 processors. This support will allow our customers to truly focus on product differentiation and perfecting their IP solutions, said Russell Crane, Sitara™ marketing manager, TI.

Quadros support for the OMAP35x with Cortex-A8 architecture includes support for the Memory Management Unit (MMU), and instruction and data caches. Cache support includes high level functions to flush and invalidate a memory area, a function to lock code or data into respective cache memory, and a set of low-level functions that allow cache operations by way/set and with cache line granularity.