RFEL adds Wideband capability to advanced channeliser IP core

"With the Wideband variant of ChannelCore Flex, you can now monitor multi-GHz bandwidths," explained Dr Alex Kuhrt, RFEL's CEO. "This enables either hardware costs to be reduced or more bandwidth monitoring to be performed for a similar system cost."

Previously, the core was limited to input bandwidths around 300MHz but this wideband input option introduces a parallel architecture supporting multi-GHz bandwidths. The input parallelism is scalable so that the practical input bandwidth limit is governed only by the available FPGA resources. RFEL has already successfully delivered a 2GHz version to a major European customer, implemented on a Xilinx Zynq 7045 device.

The core uses a novel architecture to implement a large number of Digital Down Converter (DDC) channels very efficiently. FPGA resources are used in proportion to the log of the number of channels enabling thousands of channels to be implemented in a moderately sized FPGA. 

Real-time, on-the-fly control is available for each channel to change the input source selection, centre frequency, sample rate, gain and filter response including bandwidth. There is a user programmable option to maintain phase coherency when reprogramming channels and the core is still capable of being phase coherent across multiple cores. 

Each channel has excellent RF performance with SFDR of greater than 80dBc, 80% Nyquist pass-band and a passband ripple of less than 0.1dB. A powerful fractional rate resampler is provided on each channel, allowing resampling to sub-Hz accuracy, making ChannelCore Flex a unique solution that delivers unrivalled performance using a low power budget and highly effective use of FPGA resources. The core also now supports VITA 49 timestamping.

RFEL can provide free, fully operational, fully featured cores to support system design and evaluation in either MATLAB or ModelSim. These evaluation models operate for 60 minutes before reboot allowing time for extensive evaluation of the effectiveness of the design. The time limitation is removed when the core is programmed with a key code that is provided when a full core license is purchased.

Available for Xilinx FPGAs with other devices on request, further data and pricing is available from RFEL now.