Reference flow achieves reduction in area and turnaround time

Using the integrated Cadence reference flow, the full synthesis and implementation of 5.5M instances was completed in two and a half days, which provided a significant turnaround time improvement in comparison with previous Cadence design flows. The new flow also achieved an average area reduction of three percent, while achieving a seven percent area reduction on Imagination’s most complex block.

The simple, single pass Cadence flow provides designers with guidelines to optimise their PowerVR GPU cores via documentation and scripts that are easy to deploy and support. The flow includes the following Cadence digital and sign-off tools:

• Innovus Implementation System: A next generation physical implementation tool that incorporates a parallel architecture, enabling SoC developers to deliver designs with highly competitive power, performance and area (PPA).

• Genus Synthesis Solution: An RTL synthesis and physical synthesis engine that mitigates productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times and up to 20% data path area reduction, while scaling linearly beyond 10M instances.

• Tempus Timing Sign-off Solution: A complete timing analysis tool that reduces sign-off timing closure through parallel processing and physically aware timing optimisation.

• Conformal Equivalence Checker: A widely supported independent formal verification solution enabling the verification and debug of multi-million gate designs without using test vectors.

• Quantus QRC Extraction Solution: A next generation parasitic extraction tool that is production proven and provides faster run-times for single- and multi-corner extraction.