Real Intent Shows Design Automation Functional Verification Software at Design Automation Conference

Real Intent demonstrations include:

* Ascent Family: Lint, Implied Intent Verification (IIV), PBV (X-propagation and connectivity checks) and Assertion-Based Verification (ABV)
* Meridian Family: Clock Domain Crossing (CDC) verification with innovative free running clock support and hierarchical shell model verification
* PureTime Family: new design constraint validation

Ascent is the first automatic and comprehensive software to detect and debug design errors as well as RTL and netlist simulation mismatches resulting from Xs in the design.

Explicit and implicit X sources (X assignments in Register Transfer Level (RTL) and non-resettable flops, respectively) in the designs can lead to challenging issues for design verification, such as masking real design errors and causing RTL-to-netlist simulation mismatches. Depending on coding styles, simulation results can be X-pessimistic which lead to unnecessary unknown values; or X-optimistic which results in known values when they should have been unknown. Design and verification teams write properties to trap Xs or instrument 2-value simulation with random initialization to avoid X ambiguity in order to detect design errors. However, these approaches take considerable amount of manual and computational resources without offering the complete confidence of X robustness.

Ascent PBV offers a multi-faceted solution that addresses this problem through structural and formal analysis, as well as by augmenting simulation with its SimPortal software. Explicit and implicit X sources are automatically detected. Innovative formal techniques are used to prove X-optimism safe designs. Ascent SimPortal can augment simulation to detect X-excitation, control X-pessimism, as well as eliminate X-optimism without loss of efficiency.