Real Intent Releases Ascent Lint Version 1.2 Offering New Rule Support with Low-Noise and High-Performance Linting

Ascent Lint 1.2 now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise. These rules cover the following areas:

• Legal but dubious modeling indicating probable errors

• Differences between simulation and synthesis semantics

• Naming and RTL coding conventions

• Subset restrictions to enforce modeling clarity and reduce complexity

• Opportunities to improve simulation performance

• Operations with hidden or expensive implementation costs

• Downstream tool flow issues

• Network and connectivity checks for clocks, resets, and tristate-driven signals

• Module partitioning rules

• Testability

Ascent Lint features an extremely fast engine, low noise report, and is easy to use for debugging.

“Real Intent is very focused on providing the tool chain for finding the maximum number of bugs early and economically,” commented Pranav Ashar, CTO of Real Intent, “Recognizing the importance of lint as the first and key part of this tool chain, the linter in Real Intent’s Ascent product family is tightly integrated into the HDL front end. Richer HDLs and billion-gate designs have combined to create the need for next-generation linters that understand language semantics and common programming idioms and do more than just syntax checking, all the while still delivering the high speed expected of a linter. Ascent Lint 1.2 is unique in the industry in terms of delivering this combination of speed, comprehensiveness and configurability.”