RC extraction tool accelerates design signoff

Quantus QRC Extraction solution leverages the high-accuracy modeling engine from Cadence’s previous-generation QRC Extraction product, ensuring direct compatibility and fully certified libraries for all foundries for existing users of QRC Extraction. The tool also provides significant enhancements to support FinFET features. It includes the same market-leading custom/analog functionality of QRC Extraction, and supports the same foundry-certified and -qualified “qrctechfiles.”

The solution supports both SoC and custom/analogue designs and includes a new foundry-certified integrated random-walk field solver called Quantus FS, which is up to five times faster and provides better throughput versus competing solutions. An automated incremental extraction capability reduces design closure turnaround time with up to an additional 3X performance improvement with Cadence Encounter Digital Implementation System and Tempus Timing Signoff solution. In-design signoff methodology has been enhanced in both Encounter and Virtuoso platforms.

Quantus QRC Extraction solution is proven to have the tightest correlation to foundry golden data at TSMC versus competing solutions. Its accuracy and FinFET functionality have also been certified at TSMC.

“Our customers have emphasised that it is imperative for a signoff parasitic extraction tool to provide the highest accuracy with the fastest turnaround time to ensure timely design closure,” comments Anirudh Devgan, Senior Vice President, Digital & Signoff Group, Cadence. “Quantus QRC Extraction solution has been proven to provide best-in-class accuracy for FinFET designs and deliver significantly better performance versus competing solutions.”

Quantus QRC Extraction solution is available now.