Rapid Silicon launches Vega eFPGA IP

Its customisable and scalable architecture allows the design of custom eFPGA IP from 1.5K to 100K+ Logic Cells, configurable BRAM and DSP MAC tiles. The eFPGA IP also comes with IO tiles covering all sides of the IP for easy SoC integration. The Vega IP also includes FPGA configuration block for easy eFPGA configuration and can be configured with different combinations of CLB, BRAM and DSP tiles.

"We are thrilled to launch our Vega eFPGA IP," said Naveed Sherwani, CEO of Rapid Silicon. "With its highly configurable architecture, customers can tailor the Vega IP to meet their specific needs. The Raptor Design Suite makes it easy for customers to integrate the IP into their SoCs, reducing time-to-market and development costs. We are excited to see the innovative solutions our customers will create with the Vega eFPGA IP."

The product is built based on foundry-specific standard cells, which makes it easier to port to different foundry and technology nodes. It is easy to embed into a SoC and comes with configurable input/output, clocking, and test/DFT pins. Vega IP also comes with soft FPGA configuration logic and can be integrated with SoC using JTAG or APB interface. Vega IP has an internal power grid which can be connected to the customer’s digital SoC power grid. It is highly configurable and can be ported easily to other technology nodes.

The product license comes with Raptor Design Suite - the industry's first and only commercially available open-source toolchain for FPGA. It has a complete FPGA design toolchain, including Simulation, Synthesis, Placement, Routing, Bitstream Generation & Configuration. Raptor has integrated LiteX and Migen IP management integration for easier IP integration. Our design suite also comes with Rapid Power Estimator for IP power estimation and RapidGPT plug-in for VSCode for FPGA design productivity improvements.