QuickLogic adds a high-speed SPI Host Controller option into its CSSP library

QuickLogic's CSSP approach blends fixed logic blocks with an array of low-power customisable building blocks (CBBs) for implementing additional standards-based or custom functions. This approach offers development teams a customisable platform that addresses the need to meet cost, battery life and PCB-space requirements, while also maintaining the flexibility to evolve designs as market demands change in the future. QuickLogic's CSSP platforms include the PolarPro and ArcticLink platform families, offering a range of options in size and capacity.

Today's wireless chipsets are available commonly with SDIO, SPI and mini-PCI host interfaces. When implemented in QuickLogic's programmable platform products, an SDIO Host Controller requires 15 customisable building blocks (CBBs), and PCI requires 6 to 9 CBBs depending on the configuration. The new SPI Host Controller requires only three CBBs and four I/Os, freeing resources on the CSSP platform for the implementation of additional functions (devices with from 8 to 240 CBBs are available in QuickLogic's range). The SPI interface is high speed and capable of operating at clock rates to 52 MHz. It comes with a low-overhead SPI software driver that can be customised for specific peripherals for higher performance.

QuickLogic's customer specific standard product (CSSP) design approach is all about giving the OEM/ODM developers choices within a standard framework, said Brian Faith of QuickLogic. The addition of the high speed SPI Host Controller to our silicon proven, system block library extends the developers' range of alternatives for connecting to high-performance peripherals such as WiFi and GPS chipsets.