Quartus II Software from Altera Delivers Up To 4X Faster Compile Times & Expands Support for 28-nm FPGAs

Additional upgrades include broadened 28-nm device support, including initial support for Altera’s SoC FPGAs, enhanced Qsys system integration and DSP Builder tools, and improved intellectual property core offerings. For a complete list of features and devices supported by the Quartus II software v12.0, visit www.altera.com/q2whatsnew.



Industry’s Fastest FPGA Compile Times

Quartus II software v12.0 maintains the industry’s fastest compile times, allowing customers to focus design team resources on innovating their designs while maximizing designer productivity. Stratix V FPGA users will achieve on average a 35 percent reduction in compile times, while Cyclone V and Arria V FPGAs users will see on average a 25 percent reduction in compile times with this software version, as compared to the company’s previous software release.



Expanded 28-nm FPGA Support

Quartus II software v12.0 broadens its support for 28-nm FPGAs, including initial support for Altera’s SoC FPGAs, which feature a hard dual-core ARM Cortex-A9 processor. Customers can select and start designing a wide range of low-cost, mid-range and high-end 28-nm FPGAs. New support includes the following:



-Programming support for Stratix V GX and Stratix V GS production devices

5SGXA7, 5SGXA4, 5SGXA3 and 5SGXA5

5SGSD5 and 5SGSD4

-Programming support for Stratix V GT FPGA

5SGTC5

-Device support for the largest Arria V GT FPGA

5AGTD7 with final pin-out

-Device support for Cyclone V FPGAs

5CEA7 and 5CGTD7

5CEA9, 5CGXC9 and 5CGTD9

-Compilation support for Cyclone V SX SoC FPGA

5CSXFC6D6



Qsys System Integration Tool Adds AXI-3 Interface Support

Also with this release, Altera is adding support for the ARM AMBA AXI-3 interface in its Qsys system integration tool, giving users the flexibility to connect IP cores and IP sub-systems based on different standard interfaces. Qsys is the FPGA industry’s first system integration tool based on network-on-a-chip technology, delivering users a high-performance interconnect. The tool eases system development by integrating IP functions and IP subsystems using a hierarchical approach. The latest release includes several new ease-of-use features that provide additional automation to system designers and simplifies design reuse.



Additional Features in the Quartus II Design Suite Include:



-New digital signal processing support with DSP Builder v12.0—Communicates with DDR memories from MATLAB via System Console and uses new floating-point functions for improved design productivity and greater DSP efficiency.

-Improved Video and Image Processing Suite and Video Interface IP—Eases development of video processing applications through an updated Scaler II MegaCore function with edge-adaptive algorithm and new Avalon-Streaming Video Monitor and Trace System IP cores.

-Enhanced Transceiver Design and Verification—Updated transceiver toolkit support for Arria V FPGAs and support for higher speed transceiver data rates (up to 14.1 Gbps in Stratix V FPGAs).



“From design planning to compilation to implementation, Altera makes the design process easier with the Quartus II software,” said Vince Hu, vice president of product and corporate marketing at Altera. “With our 12.0 release, customers can take advantage of faster compile times and expanded device support to meet today’s system performance requirements and productivity demands, especially for 28-nm design projects.”