Portfolio shortens design cycle & improves predictability
Cadence Design Systems has unveiled its Allegro 16.6 portfolio, which features several product and technology introductions. Driven by increasing demands to provide a more predictable and shorter design cycle, the Allegro 16.6 portfolio includes more capabilities that accelerate routing and tuning for high-speed interfaces such as DDR3 and DDR4.
Included in this release is the Allegro PCB Designer Manufacturing Option, which can shorten the time to create manufacturing documentation by up to 60%, and several key technology updates catered to increase efficiency, control and productivity for designers, while streamlining handoff to manufacturing.
The Allegro PCB Designer Manufacturing Option is a comprehensive, easy-to-use toolset that makes it efficient and cost effective for PCB designers to streamline the development of a release-to-manufacturing package for their products. It includes the Design for Manufacturing (DFM) Checker, Documentation Editor and Panel Editor modules. The Documentation Editor module can speed up overall fabrication documentation by up to 60%.
Cadence's Allegro Rules Developer and Checker allows users to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an OEM. The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks within a PCB.
The Allegro 16.6 technology portfolio update offers multiple capabilities that boost turnaround time by shortening design cycles, accelerating timing closure and providing more editing control. These capabilities include adding return path vias while routing differential pairs, ensuring a ground current return path for differential pair vias, updates to avoid coupling of high-speed signals to the FR-4 fabric weave, adjusting spacing for signals in interfaces such as DDR3 and DDR4, and a shape-editing AppMode, allowing users to create and modify complex shape geometries very easily and quickly for copper shapes, flex cover lay geometries and complex pad shapes.
“We use Cadence software for designing PCBs from concept to production for our SGI ICE X and SGI UV platforms. The technology in the Allegro PCB Manufacturing Option has enabled us to reduce the amount of time spent creating and maintaining PCB documentation by as much as 60%,” said Cassio Conceicao, COO of a client company, unspecified by Cadence. “The result is shorter design cycle times, lower costs and a smoother handoff to manufacturing.”
“The Allegro portfolio release targets critical design goals for PCB designers who are focused on increasing productivity, while operating under tight schedules and increasing complexities,” said Saugat Sen, Vice President of R&D, PCB and IC Packaging Group, Cadence. “To make the design process more efficient, Cadence introduced the Allegro Rules Developer and Checker, which provides a relational geometric verification language that enables designers to extend the standard set of rules to ones that are tailored to their needs.”