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PMC Adopts Cadence Physical Verification System as Signoff Technology for Large Complex SoC

3rd June 2013

ES Admin

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Cadence Design Systems announced today that PMC has adopted the Cadence Physical Verification System as signoff technology for its global design centers. PMC has used the Physical Verification System for several successful tapeouts, including PMC’s DIGI 120, described as the industry’s only single-chip processor supporting 10G, 40G and 100G speeds for OTN transport, aggregation and switching.

The device, with 200+ million gates and 180+ Mbits of RAM, is the largest production SoC that PMC has delivered.

“With the Cadence engineering team’s strong support, we conducted a thorough evaluation of the Cadence Physical Verification System and then integrated it into our flow,” said Colin Harris, chief operating officer and general manager of the Communications Business Unit at PMC. “It is in production use by our worldwide design teams, and the successful tapeout of our largest SoC ever confirmed that the Cadence Physical Verification System is able to manage the complexity of advanced designs with extremely fast turnaround time.”

“After years of using another product for its physical verification, PMC is seeing great success with the Cadence Physical Verification System,” said Dr. Chi-Ping Hsu, senior vice president, research and development of the Silicon Realization Group at Cadence. “With our focused commitment to signoff technology development, PMC now has a top-flight solution to help move their designs faster to manufacturing.”