PLS’ UDE 4.6.1 now supports NXP’s MPC5746R Power Architecture MCU

The high performance dual-core MPC5746R SoC, optimised for automotive engine/transmission control as well as industrial applications, offers users comprehensive features to ensure the highest level of functional safety (ASIL-D). Two Power Architecture z4 cores, running at up to 200MHz, and the eTPU timer system meet the requirements of demanding applications. A broad selection of versions, regarding Flash sizes, core configurations and packaging options, is available for the MPC5746R.

With the UDE 4.6.1, chip internal debug functions of the MPC5746R can be completely utilised for test and debugging without any limitations. As a real multi-core debugger, UDE allows entirely controlling the dual-core MPC5746R within one single debugger framework. The UDE 4.6.1’s multi-core run-control function enables an almost synchronous starting and stopping of both cores by utilising the debug logic integrated on the chip. Additionally, multi-core breakpoints employed in shared code simplify debugging of complex applications. The breakpoint always takes effect regardless of which core is currently executing the particular code. Furthermore, freely configurable perspectives within the user interface of the UDE 4.6.1 help developers to maintain an overview in a multi-core application.

For system-level analyses, the UDE 4.6.1 provides trace-based tools, which utilise the Nexus Class 3 trace capabilities of the device. Thus, not only the program flow can be recorded for post-mortem analyses. The profiling information gained by these tools can be used for runtime optimisation, for example. In addition, the UDE 4.6.1 provides the necessary code coverage to prove sufficient test coverage.

PLS’ Universal Access Device 2pro (UAD2pro) and Universal Access Device 3+ (UAD3+) ensure a fast and reliable communication of the UDE 4.6.1 with the MPC5746R. Adapters matching to the specific OnCE debug interface of the Power Architecture are available for both devices. As an option, for demanding environmental conditions, these are available with additional galvanic isolation too. Whereas the UAD2pro makes solely use of the chip’s own trace memory for the Nexus trace in order to get trace data off-chip, the UAD3+ also supports the Aurora interface. With it, large amounts of trace data can be readout from the chip with transfer rates of up to 500Mb/s, stored in the UAD3+ and then processed and analysed by the UDE 4.6.1. In the UAD 3+ up to 4 GB of memory is available.