Pixelworks Selects Uniquify’s DDR Memory Controller Subsystem IP

According to Pixelworks’ Graham Loveridge, senior vice president, strategic marketing and business development, “Uniquify has solved tricky timing and dynamic temperature problems that allow our processors to be realized in a compact form factor with a competitive price point. We also appreciate Uniquify’s eager willingness to work closely with our team to implement and debug the chip, and to share the knowledge about the DDR subsystem.”

Pixelworks selected Uniquify’s DDR Memory Controller subsystem IP because it includes Uniquify’s patented self-calibrating logic (SCL) technology for a low-power, low-area solution that automatically calibrates the DDR read timing at system power up. Read timing calibration can be the most difficult challenge in DDR memory subsystems.

The IP’s dynamic self-calibrating logic (DSCL) feature was used by Pixelworks in the most recent chip to ensure optimal timing and performance during system operation. DSCL has the ability to dynamically “tune out” temperature variation and runs during system operation to solve problems due to dynamic variation, such as temperature changes or shifts in supply voltage.

“We take great satisfaction in knowing our IP is driving the latest consumer must-have TVs and digital projectors,” notes Josh Lee, Uniquify's chief executive officer. “Pixelworks’ use of our DDR memory controller is an excellent example of the benefits of implementing adaptive IP for improved system performance and field reliability.”