PADK streamlines semiconductor package verification

Cadence will provide Amkor with PADK development support based on the Cadence Physical Verification System (PVS) software tool. This integrated solution allows Amkor’s customers to shorten the SLIM and SWIFT design and verification cycles.

“We’re at a critical juncture in the semiconductor industry with increased dependence on packaging solutions for delivery of next generation products,” said Ron Huemoeller, Amkor’s Corporate Vice President, Research and Development. “The development of these PADKs, the latest outcome of our lengthy collaboration with Cadence, addresses a critical gap forming between foundry and back-end-of-line, as fan-out packaging solutions blur the lines between these processes. Based on our vast experience with advanced package design methodologies, Amkor is well positioned to lead the industry with our unique fan-out packaging technologies.”

By jointly developing Cadence PVS-based PADKs for SLIM and SWIFT technologies, Amkor and Cadence are filling the gap between semiconductor die design and package design, while refining design methodologies for advanced IC packaging fan-out technologies. Amkor’s PADKs will enable designers to meet the design requirements needed to ensure complete package level sign-off verification for SLIM and SWIFT technologies and provide more seamless collaboration with their customers.

“To keep up with the industry’s faster performing, lower power and smaller form factor device requirements, fan-out processing is now an essential part of advanced IC packaging,” said Steve Durrill, Senior Product Engineering Group Director of the PCB Group at Cadence Design Systems. “Our partnership with Amkor fills a void when it comes to complete sign-off verification for this advanced IC packaging technology, helping to accelerate the adoption of SLIM and SWIFT technologies in this fast growing market segment.”