Orange Tree Announces Gigabit Ethernet Module With Hardware TCP/IP and Universal Interface

Mounted onto the ZestET1 is Orange Tree’s GigExpedite (GigEx) hardware TCP/IP stack including hardware UDP and TCP/IP Offload Engine (TOE). The GigEx device removes the network protocol processing burden from the CPU or companion FPGA. Resource intensive memory copies, checksum computation and reassembling of out-of-order packets are handled by the GigEx device. This allows a smaller, lower cost CPU to be deployed in the system or a soft-core processor implemented within the companion FPGA. Processor resources are allocated to running applications rather than handling network traffic.



To provide a ‘Universal Interface’ for the multiple Ethernet variations, the companion FPGA can be used to build upon the core communications protocols provided by the GigEx device (IPv4, TCP, UDP, DHCP Client, Auto IP, UPnP, HTTP, ARP). It can be quickly and cost-effectively extended to implement application layer protocols such as GigE Vision and the family of Industrial Ethernet standards. This unique capability offers the developer a common production platform that can be applied to multiple projects and multiple Ethernet standards.



“Developers in the embedded and industrial space are increasingly using Ethernet to connect smart devices to their networks at gigabit speed. But mitigating the high CPU overhead of running a full TCP/IP stack and high latency remains a stumbling block for engineers with no detailed knowledge or experience of Gigabit networking”, said Charles Sweeney, director and founder at Orange Tree Technologies. “The ZestET1 has been developed to deliver the real-time performance needed by applications such as radar, DAQ, machine vision and complex signal processing, and when compared to other Gigabit networking solutions the ET1 is delivered in a package that is low cost, easy-to-use, easy to integrate and fast to deploy.”



The on-board companion FPGA is a Xilinx Spartan-3A XC3S1400A with 1.4M system gates that are completely free for user programming. The FPGA is supported with 64MBytes DDR SDRAM, can be programmed from on-board Flash, Ethernet or JTAG and is capable of running soft-core processors and higher level protocols such as GigE Vision and Industrial Ethernet. The FPGA provides a programmable interface to external devices via the 80 pins of user IO and is used for processing and formatting of data to be streamed over the Ethernet interface. In particular the ZestET1’s use of a socket interface and register interface make it incredibly easy to use and quick to deploy. It avoids the cost and integration headache of PCI type interfacing and allows more of the FPGA logic to be dedicated to processing tasks.



Unlike software stack implementations, the ET1’s GigEx TOE offloads the entire TCP/IP protocol stack in dedicated hardware. This frees the host processor or companion FPGA to run applications, rather than handle network traffic, and delivers real-time performance capabilities. With no external processing the GigEx device is capable of saturating a Gigabit Ethernet network with data >100Mbytes/s in each direction. Its hardware acceleration increases bandwidth and reduces transfer latency to 6µseconds, helping designers meet the specifications of demanding real-time applications.



The ZestET1 defines a new OEM benchmark for Gigabit networking. Its scalability, performance, foot print, cost and ease-of-use provide a unique set of capabilities backed up by the hardware reliability of the GigEx TOE and the flexibility and programmability of the companion FPGA