Opening the door for cutting-edge electronic products

This will enable customers to deliver their products to market faster while minimising design costs and risk. TSMC also certified ANSYS solutions for the latest 7nm design rule manual and SPICE model for early design starts. Additionally, ANSYS solutions are enabled for TSMC’s Integrated Fanout (InFO), the advanced wafer level packaging technology for 3D integrated circuits.

Today's cutting edge electronic products demand minimal power yet still need to be reliable under a variety of conditions while still being affordable. These requirements place demands on the chip as well as a package, board and system. The TSMC certification provides users with a proven design process for advanced System on a Chip (SoC) – making new and innovative devices more affordable for consumers.

ANSYS design solutions support TSMC’s InFO technology to provide cost effective scaling to increase system bandwidth, reduced power consumption and smaller form factors while shortening overall design turnaround time.

TSMC's certification of ANSYS solutions for its advanced FinFET process technologies enables designers to address the power integrity and reliability requirements for any given chip. Customers will have the power to perform accurate static and dynamic voltage drop analysis and advanced signal and power electromigration verification. This empowers users to innovate the next generation of SoC designs for use in mobile, computing and networking applications.

“Certification of ANSYS solutions for TSMC’s latest technology gives our mutual customers a competitive advantage when designing complex SoCs,” said John Lee, General Manager, ANSYS. “In addition, we’re working with TSMC to expand our existing solution scope to support InFO technology, driving the delivery of advanced power integrity and reliability solutions across package, board and system levels, enabling customers to innovate at the chip package system levels.”

“Our close collaboration with ANSYS has enabled the delivery of advanced power integrity solutions including the analysis of thermal effects in FinFET technologies," said Suk Lee, Senior Director, Design Infrastructure Marketing Division at TSMC. “The certification for 10nm and 7nm, and the enablement of multiple ANSYS solutions for TSMC’s InFO packaging, ensures tool readiness for advanced FinFET technologies and allows customers to analyse and design power delivery networks for 3D-ICs with confidence.”