ML adds 5X faster verification closure to logic simulator

Using new machine learning technology and core computational software, Xcelium ML enables up to 5X faster verification closure on randomised regressions.

Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium ML learns iteratively over an entire simulation regression.

It analyses patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles.

Cadence’s Xcelium Logic Simulator provides core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload.

The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments.

“Kioxia has effectively utilised Xcelium simulation for a variety of our designs, and it addresses our ever-growing verification needs,” said Kazunari Horikawa, senior manager, Design Technology Innovation Division at Kioxia. “With the new Xcelium ML, we’ve seen a 4X shorter turnaround time in our fully random regression runs to reach 99% function coverage of original, and plan to use this technology in production designs to shorten the time to market for Kioxia’s business.”

“Xcelium ML is a powerful technology and a great example of the significant opportunity we have to leverage machine learning in verification,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “Logic simulation continues to be the workhorse of digital verification, and we are investing heavily in fundamental performance optimizations like Xcelium ML to deliver the highest verification throughput to customers using our flow.”

Xcelium ML is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.