MIT engineers grow ‘high-rise’ 3D chips

The electronics industry is nearing the physical limit for packing transistors onto a single surface of a computer chip. To overcome this constraint, chip manufacturers are increasingly exploring vertical stacking rather than traditional horizontal expansion.

Instead of cramming smaller transistors onto a single plane, the new approach involves stacking multiple layers of transistors and semiconducting materials. This strategy is likened to transforming a single-storey ranch into a multi-storey high-rise, enabling chips to process exponentially more data and perform significantly more complex functions.

However, a major obstacle is the reliance on silicon wafers, which currently serve as the primary foundation for high-quality, single-crystalline semiconducting materials. Any stackable chip design must include thick silicon layers, which can slow communication between the functional semiconductor layers.

MIT engineers have now developed a solution: a multilayered chip design that eliminates the need for silicon wafer substrates. This design operates at low temperatures, preserving the integrity of underlying circuitry.

In research published in Nature, the MIT team showcased their method for fabricating a multilayered chip. This chip alternates high-quality semiconducting materials directly grown atop each other, bypassing the need for silicon substrates.

Their technique allows engineers to construct high-performance transistors, memory, and logic components on various crystalline surfaces, rather than being restricted to bulky silicon wafers. By removing thick silicon substrates, the layers can achieve closer contact, improving communication speed and computational efficiency.

The researchers envision their method being used to create AI hardware in the form of stacked chips for laptops or wearables. These chips could rival today’s supercomputers in processing power while offering storage capacities comparable to physical data centres.

“This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” stated Jeehwan Kim, Associate Professor of Mechanical Engineering at MIT. “This could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.”

The study was co-authored by a team from MIT, including Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, along with collaborators from Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas at Dallas.

Seed pockets and low-temperature growth

In 2023, Kim’s team developed a method to grow high-quality semiconducting materials on amorphous surfaces, similar to the complex surfaces found in finished chips. They focused on 2D materials known as transition-metal dichalcogenides (TMDs), a promising alternative to silicon for creating smaller, high-performance transistors. Unlike silicon, TMDs retain their semiconducting properties even at atomic scales.

Previously, the team grew TMDs on silicon wafers with amorphous coatings. To ensure atoms arranged themselves in a single-crystalline form, the researchers used a thin silicon dioxide film patterned with tiny openings, or ‘pockets’. These pockets acted as seeds for orderly growth. However, the process required high temperatures, around 900°C.

“You have to grow this single-crystalline material below 400°C; otherwise, the underlying circuitry is completely cooked and ruined,” Kim explained. “So, our homework was to adapt the technique for temperatures lower than 400°C. If we could do that, the impact would be substantial.”

Building up with metallurgical techniques

The team refined their approach by borrowing principles from metallurgy. In metal casting, crystals form most easily at the edges of moulds, requiring less energy and heat. Inspired by this, the researchers seeded TMD growth at the edges of the silicon dioxide mask’s pockets. This method enabled them to grow single-crystalline TMDs at temperatures as low as 380°C.

The team successfully fabricated a multilayered chip with alternating layers of two TMDs: molybdenum disulfide for n-type transistors and tungsten diselenide for p-type transistors. These complementary transistors are essential for logic operations. By directly growing these materials atop each other without silicon wafers, they effectively doubled the density of semiconducting elements.

“A product realised by our technique is not only a 3D logic chip but also 3D memory and their combinations,” Kim noted. “With our growth-based monolithic 3D method, you could grow tens to hundreds of logic and memory layers, right on top of each other, and they would be able to communicate very well.”

First author Ki Seok Kim added: “Conventional 3D chips have been fabricated with silicon wafers in between, by drilling holes through the wafer – a process which limits the number of stacked layers, vertical alignment resolution, and yields. Our growth-based method addresses all of those issues at once.”

Commercialisation and future applications

Kim has since founded a company, FS2 (Future Semiconductor 2D materials), to advance the commercialisation of stackable chip designs.

“We so far show a concept at a small-scale device array,” he said. “The next step is scaling up to show professional AI chip operation.”

This research was supported by the Samsung Advanced Institute of Technology and the U.S. Air Force Office of Scientific Research.