Design
Mentor Graphics Teams with TSMC to Enrich Reference Flow 11 Low Power Verification Solutions
Mentor Graphics announced it has expanded the use of low power verification capabilities in TSMC’s Reference Flow 11 to address today’s complex integrated circuit (IC) low power functional verification requirements. The Mentor® low power verification tool suite includes the Questa® functional verification platform, the 0-In® CDC (Clock Domain Crossing) and the 0-In Formal tools and the FormalPro™ equivalence checking tool.
“M“Low power requirements are a top priority for a majority of our mutual customers,” said John Lenyo, general manager, Mentor Graphics. “That’s why effective low power design verification solutions continue to be one of our top priorities, and we intend to extend our collaboration with TSMC on future reference flow programs.”