Mentor Graphics and Samsung Optimize 14nm Process Design Kits

While cycle time is important for every process node, with the significant increase in design sizes at 14nm, continuous performance optimization of verification run times is especially critical.

“Samsung and Mentor are working closely to ensure that Calibre signoff results are both accurate and available when needed by our mutual customers,” said Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Samsung Electronics. “We use the Calibre platform as the reference tool for our design rule manual (DRM) verification, so the Calibre decks are the first ones available to our customers. Our customers need both accurate signoff to make sure their designs are ready for manufacturing, and continuously improving performance to minimize their design cycle time.”

In other collaborative efforts, Mentor and Samsung recently completed the 14nm rule deck development for the Mentor® Olympus-SoC™ place and route system, and the Olympus-SoC product was used to create a 14nm test chip with critical routing patterns for large differentiating IP blocks with representative libraries, via stack configurations, and other key parameters. Samsung has also released a 14nm process design kit for the Calibre LFD™ (Litho Friendly Design) product with specific coaching on the elimination of DFM litho errors to make fixing violations faster and more accurate.

“We engage with Samsung at the earliest stages of process qualification and work right on through to volume production at each process node,” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “There are many opportunities to add value for our mutual customers as we fine tune the design flow for better functionality, higher accuracy and faster performance.”