Mentor announces support for Samsung Foundry's 10nm FinFET process

These tools have been optimised and certified so that SoC designers can quickly adopt Samsung Foundry’s advanced 10nm process with greater confidence in first-pass success.

The interplay between design styles and manufacturing processes becomes even more critical at 10nm, so Design for Manufacturability (DFM) tools play a critical role in the verification flow. Samsung Foundry has certified the Calibre YieldEnhancer product —and specifically its SmartFill and ECO/Timing-Aware Fill capabilities — to help designers make multiple design changes and still comply with manufacturing planarity requirements and tape-out schedules.

To help designers identify and fix potential lithography-related issues, Samsung supports the use of the Calibre LFD tool, which is based on Mentor’s production-deployed solutions for process-window modeling, mask synthesis, optical proximity correction (OPC) and resolution enhancement (RET).

As design teams address multiple DFM elements simultaneously, they can use the Samsung DFM scoring and analysis solution built on the Calibre YieldAnalyzer tool to streamline the process of making tradeoff decisions. Finally, for fast feedback from manufacturing results to customer design processes, Samsung supports yield detractor pattern identification and repair using the Calibre Pattern Matching solution.

For physical verification, the Calibre nmDRC platform is now certified for 10nm and remains the ecosystem’s touchstone sign-off solution for Samsung R&D, IP validation and fabless customer design tape-outs. This release marks the culmination of years of collaboration in manufacturing process development for triple patterning and quadruple patterning with Calibre Multi-Patterning technology.

Samsung Foundry has also certified the Calibre xACT product to deliver detailed accuracy and high throughput for parasitic extraction at 10nm. The Calibre xACT tool uses an integrated field solver to calculate parasitics around the complex, three-dimensional FinFET structures. It optimises performance through a highly scalable parallel processing approach.

Other certifications help SoC designers complete circuit verification, physical implementation and IC test. For example, the AFS platform is certified in Samsung’s 10nm process device models and design kits. Mutual customers rely on AFS to deliver nanometer SPICE accuracy faster than traditional SPICE simulators for verifying analogue, RF, mixed-signal, memory and custom digital circuits.

The Olympus-SoC place and route platform is also certified for use at 10nm, with a comprehensive colored design methodology covering floorplanning, placement, extraction, routing and chip finishing requirements. To address the particular challenges of FinFET manufacturing, the platform supports M1 triple patterning, colour shifting, non-uniform tracks, mask- and width-dependent spacing rules and other new capabilities. Active deployment is underway at multiple mutual customers.

For test, Mentor and Samsung have collaborated to make the Tessent test product suite deliver higher test quality for new cell-internal structures at 10nm, as well as higher test pattern compression to control the cost of testing larger 10nm designs. The companies are also leveraging production test diagnosis to quickly identify and eliminate design-specific and cell-internal yield limiting features during design ramp-up.

“Our collaboration with Samsung Foundry goes beyond helping bring this advanced process to joint customers,” stated Joe Sawicki, Vice President and General Manager, Mentor Graphics Design to Silicon Division. “The joint solution spans design verification, manufacturing, and test to provide a high-integrity bridge between fabless companies and the Samsung foundry.”