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Maia is primarily targeted at hardware engineers who write and need to verify their own RTL code, but a key benefit of the tool is that it can be used by staff who have no knowledge of Verilog or VHDL, and who have only minimal programming skills. Modules and subsystems can be verified by anyone who has access to a specification, and who can construct sequences of vectors corresponding to the device inputs, and expected outputs.



“Module verification is normally carried out by the same hardware engineer who designed the module. The engineer is expected to hand over a working module,” commented Evan Lavelle, CTO of Maia EDA. “However, engineers are not usually programmers, and are unlikely to have the mindsets, or the time, which are required to create complex and exhaustive verification programs. The result is frequently that FPGAs are tested and debugged in-system, and ASIC developers have to buy complex system-level verification tools to find problems that should have been caught at a lower level. It's also a fact that most engineering companies don't have the resources to hire dedicated verification staff anyway. This is where Maia fits in.”



Maia automates the creation of testbenches by using declarative and fifth-generation language (5GL) techniques. An expected 'solution' is specified by listing sequences of inputs and expected outputs as vectors. Maia treats the vectors as constraints, and creates the corresponding self-checking testbench, automating the processes of driving and testing timed device inputs and outputs, clock and reset generation, stability checking, pipeline handling, internal signal probing and forcing, time handling, and error reporting.