Magma and SynTest Integrate DFT into RTL-to-GDSII Design Flow to Increase Designer Productivity

“This fully integrated IC design flow means we can handle large, complex designs through final tapeout with ease, and reduce development cycles,” said Josh Lee, president and chief executive officer of Uniquify. “It has clear benefits for designers because it preserves Magma’s productivity advantages in verification and low power, as well as in SynTest’s strengths in debug, diagnosis and ATE links.”

By combining Magma’s Talus Design RTL synthesis tool with DFT PRO Plus, design teams have a seamless link between fast, high-capacity logic synthesis and fast turnaround from register transfer level (RTL) through DFT analysis, insertion, test generation and verification. It includes a scan insertion capability using Talus Design, and exhaustive DFT analysis and auto-fix using SynTest TurboCheck-RTL/Gate. The integration adds an IEEE-compliant boundary-scan insertion, as well as memory BIST using SynTest TurboBSD and TurboBist-Memory, respectively. The integration gives design teams using Talus Design a seamless way to connect to SynTest’s VirtualScan™ ATPG test-vector compression technologies to generate XtremeCompact™ manufacturing vectors for commercial testers.

“We use Magma’s Talus RTL-to-GDSII tools and SynTest’s test technology extensively in developing our latest devices,” said Jacques Martinella, vice president of engineering of Sigma Designs. “This new tighter integration of SynTest’s test technology in the Magma IC design flow will enable us to improve our productivity and turnaround times while providing new capabilities that help us improve the testability of our advanced designs.”

For more information on the Magma and SynTest flow, visit Magma in booth 602, SynTest in booth 522 or Uniquify Inc. in booth 177 at the 47th Design Automation Conference (DAC) June 14-16 at the Anaheim Convention Center in Anaheim.