Magma Delivers Hierarchical Reference Flow for the Common Platform Alliance’s 32/28-nm Low-Power Process Technology

The hierarchical reference design was implemented using Magma’s Talus RTL-to-GDSII flow and the latest ARM Artisan® 32/28-nm LP libraries optimized for the Common Platform 32/28LP process libraries; standard cells, memory compilers and general-purpose IOs. This successful design implementation demonstrates that the flow provides key low-power design capabilities, including an automated multiple voltage-domain design methodology, validates tool and library interoperability and facilitates rapid user adoption through the inclusion of a sample design which can be accessed from Magma or the Common Platform alliance.

“The RTL-to-GDSII reference flow, combining Magma's software and the Common Platform alliance's 32/28-nm process technology, will enable our foundry customers to enjoy the benefits of power, performance and time to market for their advanced ICs,” said Dr. K.M. Choi, vice president of the Infrastructure Design Center, System LSI, Samsung Electronics, on behalf of the Common Platform alliance.

“A large percentage of leading semiconductor companies are already using Talus for 32/28-nm designs, and the list is growing,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “By working with the Common Platform alliance to develop this flow and reference design we reinforce our commitment to providing proven, effective 32/28-nm design solutions.”

Magma Reference Flow for Common Platform alliance 32/28-nm Low-Power Process
The Magma Reference Flow for Common Platform alliance 32/28-nm Low-Power Process is an integrated RTL-to-GDSII reference flow that is based on Talus Design, Talus Vortex, Hydra™ and Talus Power Pro. It provides a comprehensive low-power hierarchical solution. Talus Design and Talus Vortex provide an advanced IC implementation solution that performs timing optimization concurrently during routing – rather than sequentially before and after place and route – providing faster overall design closure with better performance and predictability. Hydra is a hierarchical design planning solution for large systems on a chip (SoCs) and features out-of-the-box reference flows for enhanced ease of use and faster delivery of better floorplans. Talus Power Pro supports power optimization techniques required in low-power designs, including multiple voltage domains, which enable the optimal tradeoff between performance, area and power, and clock gating for dynamic power reduction. Talus Power Pro supports both the Unified Power Format (UPF) and Common Power Format (CPF) standards for power intent.