Leti-UTSOI2 available in all major SPICE simulators

The Leti-UTSOI2 also includes a full description of the creation of an inversion layer at the rear face of the silicon film. This physical description is based on an original and non-simplified resolution of the equations that govern the electrostatics of the transistor. The updated model is the first compact model exhibiting this capability. It also can describe transistor behaviors in a large range of polarization applied both at the front and at the rear interface of the transistor.

“Enlarging the back biasing range accessible to the design community is key to optimizing the trade-off between performance and power consumption for UTBB technology,” commented Thierry Poiroux, research engineer at Leti and model co-developer. “This provides more opportunities to utilize FDSOI’s advantages for mobile devices and other applications that require efficient energy use.”

Exhibiting several major advantages for advanced technology nodes, FDSOI allows an electrostatic control by the gate on the channel of the transistor that is significantly better than conventional architectures. This control improves the trade-off between performance and power consumption at the circuit level, and enables significant improvements in silicon chip miniaturization. FDSOI is also a planar technology which makes the transition from conventional technologies easier, and allows significantly simplified manufacturability compared to FinFET technology.

The Leti-UTSOI2 compact model was developed to describe the electrical behavior of FDSOI transistors by taking into account all their specificities. The model is based on a physical description of the device and all the parameters are physically based, which also allows its use for predictive analysis of the process. The electrostatic coupling between the front and rear interfaces of the thin silicon film is part of the model. As a result it is particularly adapted to represent the behavior of the devices in low-doped, thin-silicon technologies in insulator layers ranging in thickness from nanometers to hundreds of micrometers.

The first version of Leti-UTSOI, valid for low-to-moderate back bias (up to Vdd),  has already been implemented. It is available in major SPICE simulators (Agilent, Cadence, Mentor Graphics and Synopsys) and it is also available in industrial process-design kits through the CMP.