Design
Lattice Updates Software Design Tools for Hot Swap Control and Power Management
Lattice Semiconductor Corporation has announced Version 5.2 of its PAC-Designer mixed signal design tool suite with new device support and productivity features. The PAC-Designer 5.2 software now supports two new higher performance Power Manager II products: the ispPAC®-POWR1014-2 and ispPAC-POWR1014A-2 devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap control, voltage rail supervision and power supply sequencing ICs. PAC-Designer 5.2 software also supports an expanded input operating frequency range of 40-400MHz for ispClock™5400D devices and a new graphical editor for phase and time skew programming.
LattBy adding Active-HDL to the PAC-Designer software verification flow, Lattice has provided a high-quality simulation and verification solution for their power management product line. Logic targeted to the PLD block of a Lattice Power Manager II family device can now be simulated with Aldec's IEEE standard VHDL/Verilog single or mixed language simulators, said Dave Rinehart, Vice President of Marketing, Aldec, Inc. As an extension to our current OEM agreement, all Aldec simulation products, including the Active-HDL Lattice Web Edition, now include support for the Lattice Power Manager II family at no cost to Lattice customers.
Power Manager II devices are commonly used to integrate discrete ICs for power management such as voltage supervisors, reset generators, watchdog timers and Hot Swap controllers. By adding HDL export features to PAC-Designer software, power supply sequencing, reset signal distribution, and other digital logic integrated into a Power Manager II device can be modeled with IEEE industry standard Verilog HDL or VHDL. PAC-Designer and Active-HDL Lattice Web Edition software can be downloaded for free from: www.latticesemi.com/products/designsoftware/pacdesigner
PAC-Designer software remains an important reason why engineers continue to adopt Lattice power management and programmable clock devices. Our design environment is very easy to use and it offers both analog and digital specialists the ability to complete designs quickly and confidently, said Chris Fanning, Lattice Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions. PAC-Designer 5.2 software supports the expanded performance of the POWR1014/A-2 and ispClock 5400D devices, which lowers cost and provides more hardware flexibility. The PAC-Designer interface to Active-HDL allows designers to use one of the market's most effective EDA tools for HDL simulation.
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