Lattice Improves Synthesis And Power Optimization In CPL Design Tools

Synplify Pro HDL Analyst provides designers a way to rapidly visualize high-level register transfer level (RTL) Verilog or VHDL. Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is the most efficient for the target CPLD. Finite State Machines (FSM), for example, are popular functions designed into CPLDs. FSMs are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings.



To minimize the dynamic power consumption of ispMACH 4000ZE CPLDs, the Classic 1.4 fitter now automatically enables the device’s Power Guard feature for unused I/O and clock resources to avoid unnecessary internal switching. The ispLEVER Classic 1.4 software also includes improved features and educational material for the popular ispMACH 4000 CPLD family. The synthesis interface to the 4000 family has been upgraded with additional optimization control and a means to reference a Synplify Design Constraints (SDC) file for timing objectives. The ispLEVER Classic software Online Help has been expanded to make designing with Lattice CPLDs even easier and more efficient. Online Help now includes links to key technical “How To” topics for ispMACH 4000 architectural features and power estimation. A new “generic” schematic library manual describes logic symbols that are portable across SPLD and CPLD device families. The Classic 1.4 design software is bundled with the ispVM™ System 17.8 programming environment.



Designers can quickly download, for free, ispLEVER Classic for Windows, as well as the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules from:

www.latticesemi.com/products/designsoftware/isplever/ispleverclassic.