IP for PCI Express 5.0 specification on TSMC N5 process

Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market.

The Cadence IP for PCIe 5.0 architecture offers a highly power-efficient implementation of the standard, with several evaluations from customers indicating it provides industry power at the maximum data transfer rate of 32GT/s and worst-case insertion loss. Leveraging Cadence’s existing N7/N6 silicon validated offering, the N5 design provides a full 512GT/s (gigatransfers per second) power-optimised solution across the full range of operating conditions with a single clock lane.

In conjunction with Cadence’s low-latency Controller IP for Compute Express Link (CXL), the Cadence PHY IP for PCIe 5.0 technology enables a new class of applications for cache-coherent interconnects for processors, workload accelerators and memory expanders, as well as support for a wide range of Ethernet protocols. This provides flexible use cases for systems that need to leverage the same IP for the networking class of applications.

“We are pleased to see Cadence expanding its IP family to support the PCIe 5.0 protocol on TSMC’s advanced processes,” said Suk Lee, Vice President of the Design Infrastructure Management Division at TSMC. “Our close collaboration with Cadence will help our mutual customers meet the stringent power and performance requirements and accelerate silicon innovation with leading-edge design solutions benefiting from TSMC’s advanced technologies.”

“Increasingly, our customers are demanding not just point IP, but total solutions that provide an edge by shortening development timeline and accelerating end-product deployment. The addition of the ultra-low power PCIe 5.0 solution to our portfolio of high-performance IP on the TSMC N7/N6, N5 and N3 technologies fulfills this need,” added Sanjive Agarwala, Corporate Vice President and General Manager of the IP Group at Cadence. “Our close collaboration with TSMC ensures that we can continue to develop advanced IP on TSMC’s most advanced processes.

“We’ve been a key provider of leading-edge PHY IP for more than 10 years and have one of the most experienced PHY design teams in the industry. Developing a solution with such low power for PCIe 5.0 architecture is a testament to the innovation our engineering teams can bring to bear to support our high-performance customer base.”

“Cadence’s PHY and controller test chips for PCIe 5.0 showed robust performance in compliance tests on our Xgig exerciser and analyser platform,” said Tom Fawcett, Vice President and General Manager, Lab & Production Business Unit, VIAVI Solutions. “Collaboration with industry leaders and visionaries like Cadence is the key to building ecosystem confidence in—and rapid adoption of—the new protocol.”

The Cadence IP for PCIe 5.0 architecture supports the company’s Intelligent System Design strategy, which enables advanced-node SoC design excellence. Cadence’s comprehensive portfolio of design IP solutions in the TSMC advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions.