IP Core exchanges data between EEPROM and CPU’s RAM

Making the contents accessible to the CPU in the same manner as a common SRAM, a READY input is required to expand the time access. Additionally, DCD's IP Core implements configurable SPI parameters like serial clock prescaler, SPI mode, CS hold/setup.

With the IP Core, the EEPROM is being connected to the CPU through the DEEPROM. The controller automatically sends all control instructions and read/write memory locations. Also, the DEEPROM is visible and can be controlled as parallel SRAM with long access time.

CD's IP Core has been developed to ensure the most accurate data flow: it was designed to be very small and efficient, with no internal tri-state buffers and signals IP Core. Additionally, it was designed in accordance with the JEDEC specification, as well as all other relevant industry standards.

Jacek Hanke, CEO, Digital Core Design, commented: "Our proprietary core allows you to map serial EEPROM in processor memory space and control it as the parallel memory. DEEPROM’s big advantage is that the core has been designed to operate with popular 25XXX SPI Serial EEPROMs from Atmel, Microchip."