Interconnect Workbench analyses and verifies ARM-based SoCs

31st October 2013

Nat Bowers

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Cadence Design Systems introduce the new Cadence Interconnect Workbench, a software solution providing cycle-accurate performance analysis of interconnects throughout the system-on-chip design process. Quickly identifying design issues under critical traffic condition, Interconnect Workbench enables users to improve device performance and reduce time to market. Working with Cadence Interconnect Validator, Interconnect Workbench offers a complete functional verification and performance validation solution.

“System designers need the cycle-accurate analysis that Interconnect Workbench provides to make trade-offs and enhance their designs,” comments Andy Nightingale, director, System IP Products, Processor Division at ARM.

Reducing the time and effort commonly needed to create a test environment that previously required several weeks, Interconnect Workbench automatically generates a performance testbench that incorporates Interconnect Validator and a complete suite of AMBA Verification IP. Allowing users to compare potential architectures side by side on one screen, Cadence Interconnect Workbench significantly boosts design performance.

Ziv Binyamini, corporate vice president of System and Verification Solutions, System and Verification Group at Cadence, commented: “Interconnect Workbench is specifically targeted at addressing the complexity of today’s SoCs. In addition to optimizing performance of their ARM-based mobile, consumer, networking and storage SoCs, users can also get their designs to market much faster.”