Questa functional verification platform with the iSDV

“To fully verify our high performance SoC bus fabric subsystems, we have to generate all kinds of complex traffic scenarios. Using Questa’s intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule,” said Galen Blake, Altera senior verification architect. “With Questa iSDV we can run embedded C test programs with RTL level testbenches allowing us to fully verify our system under stressful, but realistic, operational conditions, giving us the highest degree of confidence.”

The Questa iSDV technology addresses a common challenge encountered by many engineering teams verifying multi-core SoC designs. As processors, memory, interconnect and peripherals are assembled, creating system level test programs is complex and time-consuming. Manually writing directed tests in C is not scalable, and constrained random testing in C is not practical. As a result, most verification teams jump straight to hardware/software co-verification or worse yet, to the prototype lab, missing a critical phase of verification.

“Writing embedded test programs manually is difficult, but jumping from a handful of tests straight to booting an OS, loading drivers and running software applications is like going from the desert to drinking from a fire hose,” said Mark Olen, verification solutions technologist, Mentor. “Questa iSDV bridges the gap between IP block and full system level verification by successfully applying intelligent testbench automation at the system level.”

While writing directed tests in C to verify single-core designs at the system level is challenging, today’s multi-core, multi-threaded designs have made this process virtually impossible. Questa iSDV automates this process, creating embedded test programs that run in either the Questa verification or Veloce® emulation environments offering scalability across engines.