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Innovus implementation system qualified on Samsung 10nm FinFET process

17th February 2016

Jordan Mulcare

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Cadence Design Systems has announced that the Cadence Innovus Implementation System has been qualified for Samsung Foundry’s latest 10nm process. The Innovus Implementation System is a next-gen physical implementation tool with integrated signoff engines that have been validated for Samsung designs, providing customers with the fastest path to implementation and closure and optimal Power, Performance and Area (PPA).

The Innovus Implementation System offers customers key technologies for using the Samsung 10nm process including the GigaPlace solver-based placement technology, a slack-driven, pin access-aware placer that improves electrical and physical design convergence at advanced nodes.

The tool also offers integration with the Cadence Quantus QRC Extraction Solution, the Tempus Timing Signoff Solution, the Voltus Power Integrity Solution and the Physical Verification System, all of which enable design convergence for faster design closure. The Innovus Implementation System incorporates a massively parallel architecture that increases capacity and drives better turnaround time without compromising PPA.

“We have collaborated with Samsung to enable customers to deploy production flows on 10nm FinFET designs in order to achieve the best PPA and overcome design complexity to meet aggressive time-to-market demands,” said Dr. Anirudh Devgan, Senior Vice President and General Manager of the Digital and Signoff Group, Cadence. “We are actively working with customers on new designs on the Samsung 10nm process using the Innovus Implementation System and we are seeing early successes that can enable these designers to stay in front of the competition.”