Industry’s first verification IP for PCI Express 4.0

21st May 2014

Nat Bowers

0 0

Cadence Design Systems has introduced what the company claims to be the industry’s first verification IP (VIP) supporting PCI Express (PCIe) 4.0 architecture. This VIP enables designers to quickly and thoroughly complete the functional verification for their system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.

Susan Peterson, Director of Product Marketing, VIP Group, Cadence, commented: "In keeping with our VIP strategy of being first to market with the latest protocols, we're announcing the industry's first PCIe 4.0 architecture, which can provide the speed boost greatly needed by server and networking products to keep up with the ever-increasing demands for data throughput. Our customers now have immediate access to our latest VIP, essential to design and verification teams looking to quickly incorporate the interface."

The PCIe 4.0 specification can deliver 16 billion transactions per second (16GT/s), doubling the speed of the previous version. The specification is at the upper limit of data transmission over copper links.

"Cadence PCIe 3.0 Verification IP has enabled us to thoroughly verify that our designs comply with the PCIe 3.0 specification, and the new PCIe 4.0 product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting multiple PCIe configurations, popular verification methodologies and simulators, Cadence VIP has enabled Ineda to support our diverse product configurations with high-quality SoC and IP verification coverage,” added Balaji Kanigicherla, Founder, CTO and Vice President of Engineering, Ineda Systems.