Fujitsu's Regression Verification Time cut by Cadence Incisive Platform by 3X

Incisive Enterprise Simulator enabled Fujitsu engineers to separately elaborate the design and testbench and then simply link the proper configuration for each test, allowing them to achieve faster regression simulation. Simulator runtime performance improved 1.5X for each test when compared to an earlier version of the simulator, and the application of a compression algorithm reduced simulation data size by more than 30X.

The powerful verification management capabilities of Incisive Enterprise Manager enabled Fujitsu to automate the permutations and combinations of design and testbench components typical in functional verification projects. The verification session input format (VSIF) file 　within Incisive Enterprise Manager was employed to precisely control and manage the simulation execution. As a result, the team eliminated error-prone manual configuration processes.

“Cadence greatly improved our productivity and predictability for SoC verification,” said Masahiro Yoshida, Network SoC Design department manager for High Performance SoC Solutions Division, the Advanced Products Business Unit of Fujitsu Semiconductor Limited. “We had high verification performance requirements for our leading-edge communication processing LSI. Working closely with Cadence experts, we exceeded those requirements on this project and plan to improve our efficiency further by applying the latest Incisive features in future projects.”

“Innovative SoC verification combines tools, methodology and know-how,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Cadence Incisive tools and methodologies help our customers improve efficiency. We deliver those tools with the most talented R&D and field engineering teams in the world who are committed to customer success.”