In-System Emulation technology VarioTAP expands to support Xilinx FPGA

“We see the trend of increasing use of FPGA based system-on-chip designs with embedded processors, high-complexity functions, and high-speed peripherals continue in the future. With VarioTAP we open up totally new opportunities for board level test and in-system programming for users of Xilinx devices with integrated PowerPC Cores”, Bettina Richter, Corporate Marketing Manager at GÖPEL electronic, is glad to announce. “These new VarioTAP models allow our customers to first program the FPGA and then to combine structural Boundary Scan tests, dynamic emulation tests, mixed-signal tests, and Flash in-system programming in one platform. This concept not only improves the JTAG/Boundary Scan fault coverage considerably, but also enables significant cost reductions in production test.”

The two new VarioTAP® IP Models, supporting the PowerPC405 Core integrated in Virtex-II Pro and Virtex-4 FPGA, and the PowerPC440 processors in Virtex-5 FXT FPGAs, were developed in close cooperation with the company iSYSTEM, who joined the GOEPEL partner program GATE™ about a year ago. Control over the cores can be gained through a separate JTAG debug interface or through the native JTAG TAP of the Xilinx FPGA, enabling processor controlled Flash programming as well as a wide variety of emulation test functions.

The adaptive streaming of TAP signal pattern creates the opportunity to execute emulation tests and Boundary Scan tests in parallel or interactively within one test program, without a limit of the number of supported TAPs. Utilising the hardware platform SCANFLEX®, for example, up to eight TAP can be controlled independently and simultaneously with other I/O resources. Scripts for Flash programming are generated automatically. In addition to the execution of customer specific program code, IP functions for bus emulation and system emulation tests enable functional tests of On-Chip interfaces and externally connected periphery without the need for prior firmware download.

In order to use VarioTAP®, the user does not need any specific background knowledge, additional development tools, or processor specific Pods, simplifying the handling and ensuring ease of use.
Through OEM cooperation with all leading vendors of In-Circuit-Testers (ICT), Manufacturing Defect Analyzers (MDA), Flying Probe Testers (FPT), and Functional Testers (FCT), these new capabilities are available immediately for production tests with such test equipment.

The new VarioTAP® IP Models are supported by the Boundary Scan software SYSTEM CASCON™ Version 4.5.3, in combination with Boundary Scan controllers of the SCANBOOSTER® series and the SCANFLEX® hardware platform. The models are enabled by the software’s license manager just like any of its other features. SYSTEM CASCON™ is a professional JTAG/Boundary Scan development environment, developed by GOEPEL electronic, featuring currently more than 40 fully integrated ISP, test, and debug tools.