Imperas RISC-V reference models for verification

The OpenHW Group CORE-V Design Verification (DV) test plan is available together with the UVM testbench GitHub repository.

Processor verification has 4 key parts (1) a DV plan, (2) the tests to run, (3) a device-under-test (DUT) to test, and (4) a reference model for comparison with discrepancy debug and resolution.

Within the DV plan a number of metrics are used to record and monitor the overall progress, and in order to ensure a smooth conclusion, one of the key steps is the routine analysis and resolution steps as faults are identified and resolved. Only with a full and complete accounting as all the steps are completed can a DV team collaborate and complete the tasks within a timely and efficient timescale.

A common processor DV technique to test the complex states and extreme corner cases is to employ a random instruction stream generator, such as the popular Google open source project, RISCV-DV ISG as a test source and can be found on GitHub here. By setting up the SystemVerilog test environment to run the tests in a side-by-side configuration, with the DUT and reference model, a step-and-compare methodology can be enabled.

This avoids the inefficiencies of logfile based methods and supports direct analysis of any issues found. As a processor has a complex state-space, a step-and-compare approach also supports advanced techniques with dynamic testbenches using UVM (Universal Verification Methodology) and SystemVerilog stimulus/response features.

“The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption,” said Rick O’Connor, Founder and CEO at OpenHW Group. “Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.”

“Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog,” said Steve Richmond, Verification Manager at Silicon Laboratories and also Co-chair of the OpenHW Group Verification Task Group. “The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.”

Jingliang (Leo) Wang, Principal Engineer/Lead CPU Design Verification at Futurewei Technologies and also Co-chair of the OpenHW Group Verification Task Group, said: “The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores.

“The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution. The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.”

“As the momentum builds around open source hardware, the OpenHW Group is providing a forum for leading commercial firms to collaborate on the verification of RISC-V processor IP cores,” added Simon Davidmann, CEO at Imperas Software. “With focused resources and expert methods, the collective group effort is set to achieve tape-out quality for open source cores with full transparency on the methods, test benches and results for state-of-the-art RISC-V processor verification.”

To support the verification work of the OpenHW contributing members, Imperas has developed a SystemVerilog testbench framework which is maintained as part of the OVPworld.org library of example platforms.