Imagination announces the first RISC-V computer architecture course

Professor David Patterson, who shares the ACM A.M. Turing Award with John Hennessy for contributions to RISC, said: “RISC-V is transforming processor design and software/hardware co-design. RISC-V is an open architecture, which enables open-source hardware implementations.

"This new option means that software development can occur alongside hardware development, accelerating the design path. The RVfpga course enhances the understanding of not only RISC-V processors but also the RISC-V ecosystem and RISC-V SoCs. This course provides a deep understanding of an industrial-strength processor architecture and system of increasing popularity, which will prove useful to students throughout their academic and industry careers.”

The course is created in association with academic partners Associate Professor Sarah Harris, co-author of the popular 'Digital Design & Computer Architecture' textbook which has been published in more than five languages and is a cornerstone of courses in computer architecture, and Associate Professor Daniel Chaver.

It includes an instructor’s guide, a student manual, 10 comprehensive Labs (hands-on experiments), test materials, sample exam questions, and all the associated IP and software. To enable use in whole or in part, the source files of all the materials is provided. This flexible and open approach allows academic institutes to teach a fully featured course with the ability to augment or adapt as each teacher requires.

Associate Professor Sarah Harris, said; “RISC-V improves on previous processor generations in every conceivable way, from power consumption to performance and even increased security. As another huge step forward in computer architecture it is important for students to understand RISC-V at a fundamental level. When I was approached by Imagination to collaborate on creating this course, I was excited to bring a higher level of understanding of the technology to a wider audience, helping them get hands-on experience so that they can shape the future of computer architecture.”

Robert Owen, Director Worldwide University Programme, Imagination, said: “RISC-V is real and will pervade every computing level in the next five years. Its openness has enabled designers at all levels to get involved with processors without having to worry about licencing at the early stages of design.

"This is empowering a new generation to experiment! Up to now, academic activity has been focused on SoC design. This course is the first to provide the all-important foundation of understanding of the components of the RISC-V 'engine' and how they come together. I am delighted that the Imagination University Programme has led the creation of these materials.”

Industry support for RVfpga: Understanding Computer Architecture:

Ted Marena, Senior Director, RISC-V Ecosystem, Machine Learning Business Development at Western Digital, said: “We are pleased that the IUP is delivering the highest quality of academic material to learn the foundational details of RISC-V. It delights us that Imagination have based this course on the Western Digital RISC-V SweRV CoreTM, and that Imagination also use this core in their own IP designs. Students who complete this course will have real world commercial processor experience.”

Patrick Lysaght, Senior Director, University Program and Research Labs, Xilinx: “Xilinx FPGAs have enabled hands-on teaching and research of computer architectures for several decades. We are especially pleased to extend our support of the RISC-V open source initiative to this latest textbook and course. We believe that the combination of the RISC-V ecosystem, excellent courseware, and the opportunity to explore the SweRV core on Xilinx devices will provide a compelling educational experience for academia worldwide.”

Steve Johnson, President, Digilent Inc: “Digilent is the leader in providing FPGA development boards and instrumentation for academia. We have collaborated with Imagination on several projects, and it’s a pleasure to be supporting this initiative. We believe that RISC-V is going to have a profound impact on our industry, and we are excited to be playing a role in this new and important program.” 

Key dates:

• 3^rd September 2020, 2.55pm PDT - Associate Professors Sarah Harris and Daniel Chaver will be giving a presentation about the course at the RISC-V Global Forum
• 8^th October 2020 - The IUP will be hosting a webinar on the course, click here to register
• November 2020 - Release of the complete course in English, to be followed by Chinese, Spanish and Japanese To register your interest, join the IUP here

To date, 18 organisations including Western Digital, Xilinx, Digilent, RISC-V International and Chips Alliance are supporting the development of RVfpga.